A semiconductor manufacturing process involves the steps of exposing, etching and thin-film deposition, which steps are repeated several or a dozen times. One critical factor in those steps is defects that could be created in respective steps, and so the detection of electrical defects can be critical among others. In addition, matching (overlay) of locations between a wiring pattern formed in an under layer and a wiring pattern to be formed in an upper layer in a plurality of wiring patterns stacked one on top of the other is also critical.
It is extremely difficult for a conventional optical microscope to detect the electrical defect and it takes a long inspection period for a SEM (Scanning type Electron Microscope) to make an inspection over a large area.
Further, in such an inspection apparatus using an electron beam, an effect from charge-up in a sample surface could inhibit a clear image from being obtained. Further, in a conventional approach, the matching has been provided, for example, by making an alignment (an overlay inspection) by means of a light (an optical microscope) in conjunction with a mark of specified purpose (an overlay mark) employed for alignment of the locations between the pattern in the under layer and the pattern in the upper layer.